library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity test_tb is
end entity test_tb;

architecture structural of test_tb is


	signal	clk			: std_logic;
	signal	reset			: std_logic;
	signal	direction		: std_logic;
	signal pwm_test : std_logic;
	signal count_in :  std_logic_vector (19 downto 0);
	
begin

			

	clk		<= 	'0' after 0 ns,
		   		'1' after 10 ns when clk /= '1' else
				'0' after 10 ns;
	direction <= '1' after 0 ns,
	             '0' after 40 ns when direction = '1' else
	             '1' after 40 ns;
	reset <= '1' after 0 ns,
	             '0' after 20 ns when reset = '1' else
	             '1' after 20 ns;
end architecture structural;


